1990 search results - page 203 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
155
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SSS
2007
Springer
15 years 11 months ago
2007
Springer
System design often explores optimality of performance. What is optimal is, however, often not predefined or static in most cases, because it is affected by the context of operat...
158
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HICSS
2009
IEEE
15 years 11 months ago
2009
IEEE
The mechanisms and design principles needed for achieving optimized handoff for mobile Internet services are poorly understood and need better analysis. This paper contributes to ...
128
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HPCA
2008
IEEE
16 years 5 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
148
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ARC
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
127
Voted
ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
In this paper a 173-bit type II ONB ECC processor Section II introduces the mathematical backgrounds for for inductive RFID applications is described. Compared with curve operation...