1990 search results - page 47 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
166
Voted
TVLSI
2010
14 years 8 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
117
Voted
ISCA
2005
IEEE
15 years 7 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
106
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ACMMSP
2004
ACM
15 years 7 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
118
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IEEEPACT
2002
IEEE
15 years 6 months ago
2002
IEEE
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
104
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FAST
2007
15 years 3 months ago
2007
Abstract— Prefetching is a widely used technique in modern data storage systems. We study the most widely used class of prefetching algorithms known as sequential prefetching. Th...