1990 search results - page 83 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
159
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ICPP
1998
IEEE
15 years 8 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...
226
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IWMM
2011
Springer
14 years 6 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
153
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ARC
2008
Springer
15 years 6 months ago
2008
Springer
Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction...
145
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HIPEAC
2007
Springer
15 years 7 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...
166
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ECOOP
1995
Springer
15 years 7 months ago
1995
Springer
Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve p...