Sciweavers

1990 search results - page 92 / 398
» Optimizing the Instruction Cache Performance of the Operatin...
Sort
View
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 7 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
CODES
2000
IEEE
15 years 8 months ago
Task response time optimization using cost-based operation motion
We present a technique for task response time improvement based on the concept of code motion from the software domain. Relaxed Operation Motion (ROM) is a simple yet powerful app...
Bassam Tabbara, Abdallah Tabbara, Alberto L. Sangi...
HOTOS
2009
IEEE
15 years 8 months ago
Reinventing Scheduling for Multicore Systems
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...
Silas Boyd-Wickizer, Robert Morris, M. Frans Kaash...
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
15 years 7 months ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross
CF
2006
ACM
15 years 10 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley