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DAC
2004
ACM
16 years 5 months ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
15 years 11 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
DATE
2005
IEEE
176views Hardware» more  DATE 2005»
15 years 10 months ago
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
Linear Pseudo-Boolean Optimization (PBO) is a widely used modeling framework in Electronic Design Automation (EDA). Due to significant advances in Boolean Satisfiability (SAT), ...
Vasco M. Manquinho, João P. Marques Silva
ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
15 years 8 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
WSC
2008
15 years 7 months ago
A simulation based optimization algorithm for slack reduction and workforce scheduling
In an assembly line with high labor proportion, the workforce planning and scheduling is a very complex problem. At the background of increasing labor costs, it is very important ...
Daniel Noack, Oliver Rose