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» Optimizing the Use of High Performance Software Libraries
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LCTRTS
2010
Springer
15 years 2 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
DEBS
2009
ACM
15 years 11 months ago
Parallel event processing for content-based publish/subscribe systems
Event processing systems are a promising technology for enterprise-scale applications. However, achieving scalability yet maintaining high performance is a challenging problem. Th...
Amer Farroukh, Elias Ferzli, Naweed Tajuddin, Hans...
CCGRID
2006
IEEE
15 years 10 months ago
A Failure-Aware Scheduling Strategy in Large-Scale Cluster System
As the scale is expanding, node failure becomes a commonplace feature of large-scale cluster systems. As an important part of cluster operating system software, job scheduling tak...
Linping Wu, Dan Meng, Jianfeng Zhan, Wang Lei, Bib...
SAC
2006
ACM
15 years 10 months ago
A concurrent reactive Esterel processor based on multi-threading
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...
Xin Li, Reinhard von Hanxleden
149
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IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
15 years 10 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy