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» Optimizing the Use of High Performance Software Libraries
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HPCA
2009
IEEE
16 years 4 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
156
Voted
BMCBI
2008
211views more  BMCBI 2008»
15 years 3 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
121
Voted
JCC
2007
121views more  JCC 2007»
15 years 3 months ago
Speeding up parallel GROMACS on high-latency networks
: We investigate the parallel scaling of the GROMACS molecular dynamics code on Ethernet Beowulf clusters and what prerequisites are necessary for decent scaling even on such clust...
Carsten Kutzner, David van der Spoel, Martin Fechn...
117
Voted
MANSCI
2010
94views more  MANSCI 2010»
15 years 2 months ago
Contracting for Infrequent Restoration and Recovery of Mission-Critical Systems
Firms that rely on functioning mission-critical equipment for their businesses cannot a¤ord signi…cant operational downtime due to system disruptions. To minimize the impact of...
Sang-Hyun Kim, Morris A. Cohen, Serguei Netessine,...
160
Voted
MMB
2012
Springer
259views Communications» more  MMB 2012»
13 years 11 months ago
Boosting Design Space Explorations with Existing or Automatically Learned Knowledge
Abstract. During development, processor architectures can be tuned and configured by many different parameters. For benchmarking, automatic design space explorations (DSEs) with h...
Ralf Jahr, Horia Calborean, Lucian Vintan, Theo Un...