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93
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MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
15 years 1 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
110
Voted
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
15 years 1 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve
69
Voted
IPPS
2006
IEEE
15 years 3 months ago
Simulation of a hybrid model for image denoising
We propose a new model for image denoising which is a hybrid of the total variation model and the Laplacian mean-curvature model. An efficient numerical procedure to compute the h...
Ricolindo Cariño, Ioana Banicescu, H. Lim, ...
ICPP
2007
IEEE
15 years 4 months ago
Tempest: A portable tool to identify hot spots in parallel code
Compute clusters are consuming more power at higher densities than ever before. This results in increased thermal dissipation, the need for powerful cooling systems, and ultimatel...
Kirk W. Cameron, Hari K. Pyla, Srinidhi Varadaraja...
HPCA
2002
IEEE
15 years 10 months ago
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach
Power dissipation has become one of the most critical factors for the continued development of both high-end and low-end computer systems. The successful design and evaluation of ...
Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary J...