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MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
15 years 1 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
ISCA
2011
IEEE
225views Hardware» more  ISCA 2011»
14 years 1 months ago
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...
Rishi Agarwal, Josep Torrellas
ITNG
2008
IEEE
15 years 4 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
CCGRID
2001
IEEE
15 years 1 months ago
A DSM Cluster Architecture Supporting Aggressive Computation in Active Networks
Active networks allow computations to be performed innetwork at routers as messages pass through them. Active networks offer unique opportunities to optimize networkcentric applic...
Peter C. J. Graham
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 1 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg