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ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
15 years 1 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 2 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
CODES
2008
IEEE
15 years 4 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
15 years 3 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
106
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TPDS
2008
150views more  TPDS 2008»
14 years 9 months ago
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads....
Carlos Madriles, Carlos García Quiño...