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NPC
2005
Springer
15 years 3 months ago
Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64
This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to op...
Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. ...
PDP
2005
IEEE
15 years 3 months ago
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures
In this work we evaluate the implementation of a video encoder based on the 3D Wavelet Transform optimized for HyperThreading technology and SMPs. We design several implementation...
Ricardo Fernández, José M. Garc&iacu...
CODES
2008
IEEE
14 years 11 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
PPOPP
2003
ACM
15 years 2 months ago
Compactly representing parallel program executions
Collecting a program’s execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution pro...
Ankit Goel, Abhik Roychoudhury, Tulika Mitra
79
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SIGSOFT
2010
ACM
14 years 4 months ago
RT-simex: retro-analysis of execution traces
This presentation demonstrates the early results from the French ANR project RT-Simex. RT-Simex proposes a set of tools to analyze timing of parallel embedded code and trace the s...
Julien DeAntoni, Frédéric Mallet, Fr...