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APCSAC
2003
IEEE
15 years 6 months ago
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor
The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...
Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot H...
CODES
2003
IEEE
15 years 6 months ago
Tracking object life cycle for leakage energy optimization
The focus of this work is on utilizing the state of objects during their lifespan in optimizing the leakage energy consumed in the data caches when executing embedded Java applica...
Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. K...
91
Voted
INFOCOM
2003
IEEE
15 years 6 months ago
YAPPERS: A Peer-to-Peer Lookup Service over Arbitrary Topology
— Existing peer-to-peer search networks generally fall into two categories: Gnutella-style systems that use arbitrary topology and rely on controlled flooding for search, and sy...
Prasanna Ganesan, Qixiang Sun, Hector Garcia-Molin...
107
Voted
IOLTS
2003
IEEE
133views Hardware» more  IOLTS 2003»
15 years 6 months ago
Power Consumption of Fault Tolerant Codes: the Active Elements
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
IPPS
2003
IEEE
15 years 6 months ago
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
Dan Wallin, Erik Hagersten