The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...
Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot H...
The focus of this work is on utilizing the state of objects during their lifespan in optimizing the leakage energy consumed in the data caches when executing embedded Java applica...
Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. K...
— Existing peer-to-peer search networks generally fall into two categories: Gnutella-style systems that use arbitrary topology and rely on controlled flooding for search, and sy...
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
Daniele Rossi, Steven V. E. S. van Dijk, Richard P...
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...