45 search results - page 2 / 9 » Out-of-Order Instruction Fetch Using Multiple Sequencers |
MICRO
1995
IEEE
15 years 1 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces commo...
HPCA
1999
IEEE
15 years 1 months ago
1999
IEEE
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
ACMMSP
2004
ACM
15 years 3 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ISCA
2003
IEEE
15 years 2 months ago
2003
IEEE
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...