45 search results - page 3 / 9 » Out-of-Order Instruction Fetch Using Multiple Sequencers |
ISHPC
2003
Springer
15 years 2 months ago
2003
Springer
Abstract. Simultaneous Multithreading (SMT) tolerates latency by executing instructions from multiple threads. If a thread is stalled, resources can be used by other threads. Howev...
MICRO
1994
IEEE
15 years 1 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
IEEEPACT
1998
IEEE
15 years 1 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
HPCA
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing...
CC
2004
Springer
15 years 3 months ago
2004
Springer
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...