45 search results - page 4 / 9 » Out-of-Order Instruction Fetch Using Multiple Sequencers |
IJAIT
2008
14 years 9 months ago
2008
Instruction scheduling is one of the most important steps for improving the performance of object code produced by a compiler. A fundamental problem that arises in instruction sch...
ASAP
2003
IEEE
15 years 2 months ago
2003
IEEE
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
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WMPI
2004
ACM
15 years 3 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...