45 search results - page 5 / 9 » Out-of-Order Instruction Fetch Using Multiple Sequencers |
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HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
ACMMSP
2004
ACM
15 years 3 months ago
2004
ACM
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
IPPS
2003
IEEE
15 years 2 months ago
2003
IEEE
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...