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» Out-of-Order Instruction Fetch Using Multiple Sequencers
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IEEEPACT
2000
IEEE
15 years 1 months ago
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
Sang Jeong Lee, Pen-Chung Yew
CGO
2005
IEEE
15 years 3 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
GECCO
2000
Springer
112views Optimization» more  GECCO 2000»
15 years 1 months ago
Code Compaction Using Genetic Algorithms
One method for compacting executable computer code is to replace commonly repeated sequences of instructions with macro instructions from a decoding dictionary. The size of the de...
Keith E. Mathias, Larry J. Eshelman, J. David Scha...
ASPLOS
2000
ACM
15 years 1 months ago
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there ...
Allan Snavely, Dean M. Tullsen
BMCBI
2008
211views more  BMCBI 2008»
14 years 9 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle