45 search results - page 8 / 9 » Out-of-Order Instruction Fetch Using Multiple Sequencers |
SP
2010
IEEE
15 years 1 months ago
2010
IEEE
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...
MICRO
2002
IEEE
14 years 9 months ago
2002
IEEE
Convergent scheduling is a general framework for instruction scheduling and cluster assignment for parallel, clustered architectures. A convergent scheduler is composed of many ind...
JEI
2000
14 years 9 months ago
2000
Motion estimation is a temporal image compression technique, where an n x n block of pixels in the current frame of a video sequence is represented by a motion vector with respect...
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
CODES
2008
IEEE
14 years 11 months ago
2008
IEEE
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...