2423 search results - page 480 / 485 » Outlier detection in performance data of parallel applicatio... |
HPCA
2004
IEEE
15 years 9 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
DSN
2007
IEEE
15 years 3 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
114
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
MOBICOM
2003
ACM
15 years 2 months ago
2003
ACM
We consider a two-tiered Wireless Sensor Network (WSN) consisting of sensor clusters deployed around strategic locations and base-stations (BSs) whose locations are relatively fl...
103
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EUROPAR
2009
Springer
15 years 2 months ago
2009
Springer
Data access in HPC infrastructures is realized via user-level networking and OS-bypass techniques through which nodes can communicate with high bandwidth and low-latency. Virtualiz...