22 search results - page 2 / 5 » Output Prediction Logic: A High-Performance CMOS Design Tech... |
APCCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
PATMOS
2005
Springer
15 years 3 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper presents new circuit configurationsfor a more robust and efficient form of self-resettingCMOS (SRCMOS). Prior structures for SRCMOS have very high performance but are...
ISCAS
2008
IEEE
15 years 3 months ago
2008
IEEE
—In this paper, an improved method of power control is introduced to widen the range of output power with high efficiency. Two CMOS class-E power amplifiers (PA) with different o...
ISCAS
2008
IEEE
15 years 3 months ago
2008
IEEE
— This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay...