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DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
15 years 1 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka
BMCBI
2007
123views more  BMCBI 2007»
14 years 10 months ago
Metabonomics evaluations of age-related changes in the urinary compositions of male Sprague Dawley rats and effects of data norm
Background: Urine from male Sprague-Dawley rats 25, 40, and 80 days old was analyzed by NMR and UPLC/MS. The effects of data normalization procedures on principal component analys...
Laura K. Schnackenberg, Jinchun Sun, Parvaneh Espa...
BMCBI
2005
127views more  BMCBI 2005»
14 years 10 months ago
Dynamic modeling of cis-regulatory circuits and gene expression prediction via cross-gene identification
Background: Gene expression programs depend on recognition of cis elements in promoter region of target genes by transcription factors (TFs), but how TFs regulate gene expression ...
Li-Hsieh Lin, Hsiao-Ching Lee, Wen-Hsiung Li, Bor-...
HPCA
2009
IEEE
15 years 10 months ago
A first-order fine-grained multithreaded throughput model
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
Xi E. Chen, Tor M. Aamodt
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
15 years 4 months ago
Silicon neurons that inhibit to synchronize
Abstract—We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by de...
John V. Arthur, Kwabena Boahen