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» Overlay Networks - Implementation by Specification
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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
15 years 10 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ADC
2006
Springer
135views Database» more  ADC 2006»
15 years 10 months ago
Using a temporal constraint network for business process execution
Business process management (BPM) has emerged as a dominant technology in current enterprise systems and business solutions. However, the technology continues to face challenges i...
Ruopeng Lu, Shazia Wasim Sadiq, Vineet Padmanabhan...
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 10 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ITNG
2010
IEEE
15 years 9 months ago
QARI: Quality Aware Software Deployment for Wireless Sensor Networks
Abstract--If we are to deploy sensor applications in a realistic business context, we must provide innovative middleware services to control and enforce required system behavior; i...
Wouter Horré, Sam Michiels, Wouter Joosen, ...
ICCCN
1998
IEEE
15 years 9 months ago
A Two-Phase Inter-Switch Handoff Scheme for Wireless ATM Networks
Supporting mobility in Wireless ATM networks poses a number of technical issues. An important issue is the ability to reroute ongoing virtual connections during handoff as mobile ...
Khaled Salah, Elias Drakopoulos