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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 2 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
77
Voted
EDBT
2009
ACM
90views Database» more  EDBT 2009»
15 years 2 months ago
Parallelization of XPath queries using multi-core processors: challenges and experiences
In this study, we present experiences of parallelizing XPath queries using the Xalan XPath engine on shared-address space multi-core systems. For our evaluation, we consider a sce...
Rajesh Bordawekar, Lipyeow Lim, Oded Shmueli
66
Voted
TCAD
2008
84views more  TCAD 2008»
14 years 9 months ago
Buffering Interconnect for Multicore Processor Designs
Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a ...
Yifang Liu, Jiang Hu, Weiping Shi
IPPS
2010
IEEE
14 years 7 months ago
Oblivious algorithms for multicores and network of processors
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...
Rezaul Alam Chowdhury, Francesco Silvestri, Brando...
ICPP
2008
IEEE
15 years 4 months ago
Memory Access Scheduling Schemes for Systems with Multi-Core Processors
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...