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ASPDAC
2010
ACM
150views Hardware» more  ASPDAC 2010»
14 years 10 months ago
Post-silicon debugging for multi-core designs
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are ...
Valeria Bertacco
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 3 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
CLUSTER
2009
IEEE
15 years 4 months ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis
EUROPAR
2009
Springer
15 years 6 months ago
An Extension of the StarSs Programming Model for Platforms with Multiple GPUs
While general-purpose homogeneous multi-core architectures are becoming ubiquitous, there are clear indications that, for a number of important applications, a better performance/p...
Eduard Ayguadé, Rosa M. Badia, Francisco D....
NCA
2005
IEEE
15 years 5 months ago
C-CORE: Using Communication Cores for High Performance Network Services
Recent hardware advances are creating multi-core systems with heterogeneous functionality. This paper explores how applications and middleware can utilize systems comprised of pro...
Sanjay Kumar, Ada Gavrilovska, Karsten Schwan, Sri...