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ASPLOS
2010
ACM
15 years 3 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
ICSE
2010
IEEE-ACM
15 years 1 months ago
SMT-based bounded model checking for multi-threaded software in embedded systems
The transition from single-core to multi-core processors has made multi-threaded software an important subject over the last years in computer-aided verification. Model checkers ...
Lucas Cordeiro
DATE
2009
IEEE
129views Hardware» more  DATE 2009»
15 years 6 months ago
Distributed peak power management for many-core architectures
Recently proposed techniques for peak power management [5] involve centralized decision-making and assume quick evaluation of the various power management states. These techniques...
John Sartori, Rakesh Kumar
IPPS
2009
IEEE
15 years 6 months ago
Building a parallel pipelined external memory algorithm library
Large and fast hard disks for little money have enabled the processing of huge amounts of data on a single machine. For this purpose, the well-established STXXL library provides a...
Andreas Beckmann, Roman Dementiev, Johannes Single...
EUROPAR
2009
Springer
15 years 6 months ago
PSPIKE: A Parallel Hybrid Sparse Linear System Solver
The availability of large-scale computing platforms comprised of tens of thousands of multicore processors motivates the need for the next generation of highly scalable sparse line...
Murat Manguoglu, Ahmed H. Sameh, Olaf Schenk