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ASPLOS
2011
ACM
14 years 3 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 6 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
15 years 6 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
POPL
2006
ACM
16 years 3 days ago
Autolocker: synchronization inference for atomic sections
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
Bill McCloskey, Feng Zhou, David Gay, Eric A. Brew...
ICCAD
2008
IEEE
246views Hardware» more  ICCAD 2008»
15 years 8 months ago
MC-Sim: an efficient simulation tool for MPSoC designs
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
Jason Cong, Karthik Gururaj, Guoling Han, Adam Kap...