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VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
15 years 5 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
AAECC
2006
Springer
122views Algorithms» more  AAECC 2006»
15 years 3 months ago
Low-Floor Tanner Codes Via Hamming-Node or RSCC-Node Doping
We study the design of structured Tanner codes with low error-rate floors on the AWGN channel. The design technique involves the "doping" of standard LDPC (proto-)graphs,...
Shadi Abu-Surra, Gianluigi Liva, William E. Ryan
FCCM
2004
IEEE
175views VLSI» more  FCCM 2004»
15 years 3 months ago
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jo...
SIPS
2007
IEEE
15 years 6 months ago
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
CORR
2007
Springer
132views Education» more  CORR 2007»
14 years 11 months ago
Probabilistic Analysis of Linear Programming Decoding
Abstract—We initiate the probabilistic analysis of linear programming (LP) decoding of low-density parity-check (LDPC) codes. Specifically, we show that for a random LDPC code e...
Constantinos Daskalakis, Alexandros G. Dimakis, Ri...