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FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
15 years 1 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
76
Voted
IPPS
2003
IEEE
15 years 2 months ago
An Executable Analytical Performance Evaluation Approach for Early Performance Prediction
Percolation has recently been proposed as a key component of an advanced program execution model for future generation high-end machines featuring adaptive data/code transformatio...
Adeline Jacquet, Vincent Janot, Clement Leung, Gua...
78
Voted
JMM2
2007
118views more  JMM2 2007»
14 years 9 months ago
FPGA-based Real-time Optical Flow Algorithm Design and Implementation
—Optical flow algorithms are difficult to apply to robotic vision applications in practice because of their extremely high computational and frame rate requirements. In most case...
Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson
IPPS
2006
IEEE
15 years 3 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov
82
Voted
DAC
2003
ACM
15 years 2 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III