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» PAPER - Accelerating parallel evaluations of ROCS
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HPCA
2009
IEEE
16 years 5 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
HPCA
1999
IEEE
15 years 8 months ago
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory
Symmetric multiprocessors (SMPs) connected with low-latency networks provide attractive building blocks for software distributed shared memory systems. Two distinct approaches hav...
Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas ...
JCM
2010
119views more  JCM 2010»
15 years 2 months ago
Evaluation of Router Implementations for Explicit Congestion Control Schemes
— Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require ...
Simon Hauger, Michael Scharf, Jochen Kögel, C...
DAMON
2008
Springer
15 years 6 months ago
Data partitioning on chip multiprocessors
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-leve...
John Cieslewicz, Kenneth A. Ross
SPIRE
2010
Springer
15 years 2 months ago
Evaluation of Query Performance Prediction Methods by Range
During the last years a great number of Query Performance Prediction methods have been proposed. However, this explosion of prediction method proposals have not been paralleled by ...
Joaquín Pérez-Iglesias, Lourdes Arau...