2020 search results - page 194 / 404 » PAPER - Accelerating parallel evaluations of ROCS |
171
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MICRO
2007
IEEE
16 years 15 days ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
143
Voted
IPPS
2006
IEEE
16 years 7 days ago
2006
IEEE
This paper presents a helper thread prefetching scheme that is designed to work on loosely-coupled processors, such as in a standard chip multi-processor (CMP) system and in an in...
159
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IPPS
2005
IEEE
15 years 11 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
148
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IFL
2004
Springer
2004
Springer
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations
15 years 11 months ago
The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the...
128
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IPPS
2003
IEEE
15 years 11 months ago
2003
IEEE
A problem that has been getting prominence in testing is that of looking for intermittent bugs. Multi-threaded code is becoming very common, mostly on the server side. As there is...