2020 search results - page 388 / 404 » PAPER - Accelerating parallel evaluations of ROCS |
87
Voted
ISCA
2008
IEEE
15 years 6 months ago
2008
IEEE
Writing shared-memory parallel programs is error-prone. Among the concurrency errors that programmers often face are atomicity violations, which are especially challenging. They h...
81
Voted
ISVLSI
2008
IEEE
15 years 6 months ago
2008
IEEE
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
115
Voted
NDSS
2008
IEEE
15 years 6 months ago
2008
IEEE
Protocol reverse engineering has often been a manual process that is considered time-consuming, tedious and error-prone. To address this limitation, a number of solutions have rec...
75
Voted
ASAP
2007
IEEE
15 years 6 months ago
2007
IEEE
Though all of the current main-stream OSs have supported superpage to some extent, most of them need runtime information provided by applications, simulator or other tools. Transp...
CCGRID
2007
IEEE
15 years 6 months ago
2007
IEEE
Increasing power consumption of high-performance systems leads to reliability, survivability, and cooling related problems. Motivated by this observation, several recent efforts f...