In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
Klaus Buchenrieder, Andreas Pyttel, Alexander Sedl...
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jo...
A key enabling technology for the prolikration of multima dia PC’s is the availability of fast video codeca, which are the basic building blocks of many new multimedia applicati...
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
Packet loss and delay in Internet degrade the quality of requested services like VoIP (Voice over IP) or Video Streaming. In novel network scenarios where wired and wireless connec...