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ISQED
2003
IEEE
73views Hardware» more  ISQED 2003»
15 years 5 months ago
A Novel Clocking Strategy for Dynamic Circuits
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
TAP
2008
Springer
153views Hardware» more  TAP 2008»
14 years 11 months ago
Bounded Relational Analysis of Free Data Types
Abstract. In this paper we report on our first experiences using the relational analysis provided by the Alloy tool with the theorem prover KIV in the context of specifications of ...
Andriy Dunets, Gerhard Schellhorn, Wolfgang Reif
FPT
2005
IEEE
98views Hardware» more  FPT 2005»
15 years 5 months ago
Secure Partial Reconfiguration of FPGAs
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
Amir Sheikh Zeineddini, Kris Gaj
ICCD
2000
IEEE
159views Hardware» more  ICCD 2000»
15 years 4 months ago
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...
Deependra Talla, Lizy Kurian John, Viktor S. Lapin...
IISWC
2006
IEEE
15 years 5 months ago
A Quantitative Evaluation of the Contribution of Native Code to Java Workloads
— Many performance analysis tools for Java focus on tracking executed bytecodes, but provide little support in determining the specific contribution of native code libraries. Th...
Walter Binder, Jarle Hulaas, Philippe Moret