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ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 5 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
HICSS
2003
IEEE
201views Biometrics» more  HICSS 2003»
15 years 5 months ago
Design and Evaluation of Improvement method on the Web Information Navigation - A Stochastic Search Approach
With the advent of fast growing Internet and World Wide Web (WWW), more and more companies start the electronic commerce to enhance the business competitiveness. On the other hand...
Benjamin P.-C. Yen, Y.-W. Wan
IEEEPACT
2007
IEEE
15 years 6 months ago
AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors
Many sorting algorithms have been studied in the past, but there are only a few algorithms that can effectively exploit both SIMD instructions and threadlevel parallelism. In this...
Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, To...
HOTI
2005
IEEE
15 years 5 months ago
SIFT: Snort Intrusion Filter for TCP
Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention services to run at multi Gigabit/second rates. High-level intrusion rules mapped d...
Michael Attig, John W. Lockwood
ASPLOS
2000
ACM
15 years 4 months ago
Power Aware Page Allocation
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory ...
Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schl...