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2009
IEEE
15 years 7 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
IEEECIT
2010
IEEE
14 years 11 months ago
Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems
—As the need for embedded systems to interact with other systems is growing fast, we see great opportunities in introducing the hardware-in-the-loop technique to the field of ha...
Dogan Fennibay, Arda Yurdakul, Alper Sen
RECONFIG
2009
IEEE
165views VLSI» more  RECONFIG 2009»
15 years 7 months ago
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip
—We envision that future FPGA will use a hardwired network on chip (HWNoC) [14] as a unified interconnect for functional communications (data and control) as well as configurat...
Muhammad Aqeel Wahlah, Kees G. W. Goossens
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DATE
2008
IEEE
100views Hardware» more  DATE 2008»
15 years 6 months ago
A Mapping Framework for Guided Design Space Exploration of Heterogeneous MP-SoCs
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...
Bastian Ristau, Torsten Limberg, Gerhard Fettweis
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 6 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman