230 search results - page 45 / 46 » PPM Reduction on Embedded Memories in System on Chip |
GLVLSI
2005
IEEE
13 years 12 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
DATE
2008
IEEE
14 years 24 days ago
2008
IEEE
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
SAMOS
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
CODES
2009
IEEE
13 years 10 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
LCTRTS
2007
Springer
14 years 15 days ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...