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» Packet Reordering in Network Processors
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DAC
2002
ACM
15 years 10 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
123
Voted
OSN
2011
14 years 4 months ago
Performance modeling of HS-RR-TCP over load-balanced optical burst-switched (OBS) networks
TCP-over-OBS is a promising transport paradigm to support next-generation Internet. It is well-known that loadbalanced routing generally improves loss performance over OBS. We ide...
Neal Charbonneau, Vinod Vokkarane
80
Voted
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 2 months ago
A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today's dominant template, will not me...
Pierre Guerrier, Alain Greiner
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 1 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
109
Voted
INFOCOM
2006
IEEE
15 years 3 months ago
The Concurrent Matching Switch Architecture
Abstract— Network operators need high capacity router architectures that can offer scalability, provide throughput guarantees, and maintain packet ordering. However, current cent...
Bill Lin, Isaac Keslassy