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» Packet Reordering in Network Processors
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76
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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 6 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
79
Voted
HPCA
2003
IEEE
16 years 1 days ago
Active I/O Switches in System Area Networks
We present an active switch architecture to improve the performance of systems connected via system area networks. Our programmable active switches not only flexibly route packets...
Ming Hao, Mark Heinrich
ICC
2007
IEEE
15 years 6 months ago
Voice Transmission Enhancing Model on Wireless Mesh Networks
Abstract— This paper initially shows ROHC and packet aggregation significantly improve the number of successful voice calls. However, the improvement does not include processor...
Sangkil Jung, Sangjin Hong, Kyungtae Kim, Junghoon...
JCM
2010
119views more  JCM 2010»
14 years 10 months ago
Evaluation of Router Implementations for Explicit Congestion Control Schemes
— Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require ...
Simon Hauger, Michael Scharf, Jochen Kögel, C...
82
Voted
ACMSE
2007
ACM
15 years 3 months ago
CluVis: dual-domain visual exploration of cluster/network metadata
CluVis, a prototype for visual monitoring and exploration of cluster and network metadata, is introducted. CluVis builds upon interactively added charts of cluster/network metadat...
Christopher Waters, Jonathan Howell, T. J. Jankun-...