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» Packet Reordering in Network Processors
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JSA
2008
94views more  JSA 2008»
14 years 9 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
CN
1999
116views more  CN 1999»
14 years 9 months ago
Network-conscious GIF image transmission over the Internet
Traditional image compression techniques seek the smallest possible le size for a given level of image quality. By contrast, network-conscious image compression techniques take in...
Paul D. Amer, Sami Iren, Gul E. Sezen, Phillip T. ...
DSN
2008
IEEE
15 years 4 months ago
Toward an understanding of the processing delay of peer-to-peer relay nodes
Abstract—Peer-to-peer relaying is commonly used in realtime applications to cope with NAT and firewall restrictions and provide better quality network paths. As relaying is not ...
Kuan-Ta Chen, Jing-Kai Lou
FPL
2005
Springer
111views Hardware» more  FPL 2005»
15 years 3 months ago
Mutable Codesign for Embedded Protocol Processing
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
Todd S. Sproull, Gordon J. Brebner, Christopher E....
ICDE
2006
IEEE
201views Database» more  ICDE 2006»
15 years 3 months ago
Content and Context Aware Networking Using Semantic Tagging
Today’s model of networking primarily concentrates intelligence at the end hosts with the network itself offering a simple“best-effort”,“data agnostic” communication med...
Sethuram Balaji Kodeswaran, Anupam Joshi