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» Packet Reordering in Network Processors
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ICC
2009
IEEE
113views Communications» more  ICC 2009»
15 years 4 months ago
Green Support for PC-Based Software Router: Performance Evaluation and Modeling
—We consider a new generation of COTS Software Routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact o...
Raffaele Bolla, Roberto Bruschi, Andrea Ranieri
JPDC
2011
129views more  JPDC 2011»
14 years 4 months ago
Static timing analysis for modeling QoS in networks-on-chip
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Is...
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 4 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
INFOCOM
1996
IEEE
15 years 1 months ago
Congestion-Oriented Shortest Multipath Routing
We present a framework for the modeling of multipath routing in connectionless networks that dynamically adapt to network congestion. The basic routing protocol uses a short-term ...
Shree Murthy, J. J. Garcia-Luna-Aceves
LCN
2000
IEEE
15 years 2 months ago
Performance Impact of Data Compression on Virtual Private Network Transactions
Virtual private networks (VPNs) allow two or more parties to communicate securely over a public network. Using cryptographic algorithms and protocols, VPNs provide security servic...
John Patrick McGregor, Ruby B. Lee