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FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 1 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
HCW
1999
IEEE
15 years 1 months ago
A Unified Resource Scheduling Framework for Heterogeneous Computing Environments
A major challenge in Metacomputing Systems (Computational Grids) is to effectively use their shared resources, such as compute cycles, memory, communication network, and data repo...
Ammar H. Alhusaini, Viktor K. Prasanna, Cauligi S....
ER
1999
Springer
108views Database» more  ER 1999»
15 years 1 months ago
Modeling Cyclic Change
Database support of time-varying phenomena typically assumes that entities change in a linear fashion. Many phenomena, however, change cyclically over time. Examples include monsoo...
Kathleen Hornsby, Max J. Egenhofer, Patrick J. Hay...
MICRO
1998
IEEE
91views Hardware» more  MICRO 1998»
15 years 1 months ago
Effective Cluster Assignment for Modulo Scheduling
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
Erik Nystrom, Alexandre E. Eichenberger
DAC
1994
ACM
15 years 1 months ago
Automatic Verification of Pipelined Microprocessors
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
Vishal Bhagwati, Srinivas Devadas