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TCSV
2008
120views more  TCSV 2008»
15 years 4 months ago
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
Abstract--This paper proposes a parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm and applied to the SLAM (...
Vanderlei Bonato, Eduardo Marques, George A. Const...
CASC
2010
Springer
153views Mathematics» more  CASC 2010»
15 years 1 months ago
Implementing Data Parallel Rational Multiple-Residue Arithmetic in Eden
Abstract. Residue systems present a well-known way to reduce computation cost for symbolic computation. However most residue systems are implemented for integers or polynomials. Th...
Oleg Lobachev, Rita Loogen
ASAP
2009
IEEE
142views Hardware» more  ASAP 2009»
16 years 1 months ago
Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition
—Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretize...
Martin C. Herbordt, Md. Ashfaquzzaman Khan, Tony D...
ISSAC
2009
Springer
155views Mathematics» more  ISSAC 2009»
15 years 11 months ago
Parallel sparse polynomial multiplication using heaps
We present a high performance algorithm for multiplying sparse distributed polynomials using a multicore processor. Each core uses a heap of pointers to multiply parts of the poly...
Michael B. Monagan, Roman Pearce
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
15 years 10 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra