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CASES
2004
ACM
15 years 3 months ago
A hamming distance based VLIW/EPIC code compression technique
This paper presents and reports on a VLIW code compression technique based on vector Hamming distances [19]. It investigates the appropriate selection of dictionary vectors such t...
Montserrat Ros, Peter Sutton
TACAS
2010
Springer
342views Algorithms» more  TACAS 2010»
15 years 5 months ago
SAT Based Bounded Model Checking with Partial Order Semantics for Timed Automata
We study the model checking problem of timed automata based on SAT solving. Our work investigates alternative possibilities for coding the SAT reductions that are based on parallel...
Janusz Malinowski, Peter Niebert
IPPS
1996
IEEE
15 years 2 months ago
A Method for Register Allocation to Loops in Multiple Register File Architectures
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt,...
EURODAC
1994
IEEE
116views VHDL» more  EURODAC 1994»
15 years 2 months ago
A performance evaluator for parameterized ASIC architectures
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
Jie Gong, Daniel D. Gajski, Alex Nicolau
ICPP
1993
IEEE
15 years 2 months ago
Meta-State Conversion
Abstract — In MIMD (Multiple Instruction stream, Multiple Data stream) execution, each processor has its own state. Although these states are generally considered to be independe...
Henry G. Dietz, G. Krishnamurthy