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» Parallel CABAC for low power video coding
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ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
VLSISP
2008
106views more  VLSISP 2008»
15 years 4 months ago
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
Jonah Probell
ISCAS
2005
IEEE
133views Hardware» more  ISCAS 2005»
15 years 10 months ago
Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video
Abstract— The mixed-signal processor performs digital vectormatrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell ...
Rafal Karakiewicz, Roman Genov
138
Voted
CORR
2008
Springer
118views Education» more  CORR 2008»
15 years 4 months ago
The price of certainty: "waterslide curves" and the gap to capacity
The classical problem of reliable point-to-point digital communication is to achieve a low probability of error while keeping the rate high and the total power consumption small. ...
Anant Sahai, Pulkit Grover
CODES
2007
IEEE
15 years 11 months ago
Smart driver for power reduction in next generation bistable electrophoretic display technology
Microencapsulated electrophoretic displays (EPDs) are quickly emerging as an important technology for use in battery-powered portable computing devices. Thanks to bistability and ...
Michael A. Baker, Aviral Shrivastava, Karam S. Cha...