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132
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HPCA
2008
IEEE
16 years 2 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
HPCA
2005
IEEE
16 years 2 months ago
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
Youtao Zhang, Lan Gao, Jun Yang 0002, Xiangyu Zhan...
152
Voted
FMICS
2007
Springer
15 years 8 months ago
An Approach to Formalization and Analysis of Message Passing Libraries
Message passing using libraries implementing the Message Passing Interface (MPI) standard is the dominant communication mechanism in high performance computing (HPC) applications. ...
Robert Palmer, Michael Delisi, Ganesh Gopalakrishn...
CASES
2006
ACM
15 years 8 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
WOTUG
2008
15 years 4 months ago
Representation and Implementation of CSP and VCR Traces
Abstract. Communicating Sequential Processes (CSP) was developed around a formal algebra of processes and a semantics based on traces (and failures and divergences). A trace is a r...
Neil C. C. Brown, Marc L. Smith