3584 search results - page 407 / 717 » Parallel Computing of Thermoelasticity Problems |
145
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FCCM
2006
IEEE
15 years 10 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
144
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ICPPW
2006
IEEE
15 years 10 months ago
2006
IEEE
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
147
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
123
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PPOPP
2005
ACM
15 years 9 months ago
2005
ACM
Efficient partitioning of parallel loops plays a critical role in high performance and efficient use of multiprocessor systems. Although a significant amount of work has been don...
141
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IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...