5588 search results - page 131 / 1118 » Parallel Implementation of Bags |
106
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JCC
2008
14 years 10 months ago
2008
: For the new parallel implementation of electronic structure methods in ACES III (Lotrich et al., in preparation) the present state-of-the-art algorithms for the evaluation of ele...
109
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TSP
2008
14 years 10 months ago
2008
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
106
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IJCIS
1998
14 years 9 months ago
1998
We present the systematic design and development of a distributed query scheduling service DQS in the context of DIOM, a distributed and interoperable query mediation system 26 ...
ICIP
2007
IEEE
15 years 11 months ago
2007
IEEE
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...
107
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HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...