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122
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DATE
2007
IEEE
133views Hardware» more  DATE 2007»
15 years 11 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
DDECS
2006
IEEE
94views Hardware» more  DDECS 2006»
15 years 10 months ago
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description
Abstract— In this paper, we describe a system for transforming a code given in ANSI C into an equivalent SystemC description. In order to synthesize parallel C codes into hardwar...
Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic,...
ICPPW
2005
IEEE
15 years 10 months ago
Gene Sequence Alignment on a Public Computing Platform
Public computing can potentially supply not only computational power but also memory and short term storage resources to grid and cluster scale problems. Gene sequence alignment i...
Stephen Pellicer, Nova Ahmed, Yi Pan, Yao Zheng
PVM
2009
Springer
15 years 9 months ago
Multiple-Level MPI File Write-Back and Prefetching for Blue Gene Systems
This paper presents the design and implementation of an asynchronous data-staging strategy for file accesses based on ROMIO, the most popular MPI-IO distribution, and ZeptoOS, an ...
Javier García Blas, Florin Isaila, Jes&uacu...
129
Voted
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 9 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft