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FPL
2006
Springer
161views Hardware» more  FPL 2006»
15 years 8 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
WOTUG
2008
15 years 6 months ago
Visual Process-Oriented Programming for Robotics
When teaching concurrency, using a process-oriented language, it is often introduced through a visual representation of programs in the form of process network . These diagrams all...
Jonathan Simpson, Christian L. Jacobsen
WAE
2001
281views Algorithms» more  WAE 2001»
15 years 6 months ago
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. In this pa...
David A. Bader, Ajith K. Illendula, Bernard M. E. ...
IPPS
2010
IEEE
15 years 2 months ago
User level DB: a debugging API for user-level thread libraries
With the advent of the multicore era, parallel programming is becoming ubiquitous. Multithreading is a common approach to benefit from these architectures. Hybrid M:N libraries lik...
Kevin Pouget, Marc Pérache, Patrick Carriba...
ICPP
2009
IEEE
15 years 11 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...