5588 search results - page 875 / 1118 » Parallel Implementation of Bags |
127
Voted
PDP
2010
IEEE
15 years 7 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
158
Voted
ICPP
1999
IEEE
15 years 7 months ago
1999
IEEE
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...
157
Voted
IPPS
1999
IEEE
15 years 7 months ago
1999
IEEE
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
107
Voted
ICPP
1998
IEEE
15 years 7 months ago
1998
IEEE
We propose a new universal High-Level Information (HLI) format to effectively integrate front-end and back-end compilers by passing front-end information to the back-end compiler....
122
Voted
MICRO
1998
IEEE
15 years 7 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...